JAMSC-B1060硬件設(shè)計(jì)
JAMSC-B1060硬件設(shè)計(jì)設(shè)計(jì)包括了MVB控制器的FPGA設(shè)計(jì)和MVB總線系統(tǒng)的板級(jí)設(shè)計(jì),其中關(guān)鍵的MVB控制器的設(shè)計(jì)如圖5 [align=center]
圖5:JAMSC-B1060控制器的框圖[/align] 如圖所示,MVB控制器包含以下功能模塊:
●編碼器:產(chǎn)生曼徹斯特編碼,傳送數(shù)據(jù)幀
●發(fā)送緩沖區(qū):作為要發(fā)送的數(shù)據(jù)和CRC檢測(cè)值的緩沖區(qū)
●譯碼器:接收、曼徹斯特譯碼,數(shù)據(jù)提取、數(shù)據(jù)錯(cuò)誤檢測(cè)
●接收緩沖區(qū):作為接收端數(shù)據(jù)和CRC結(jié)果的緩沖區(qū)
●報(bào)文分析單元:檢測(cè)主幀和從幀超時(shí),幀誤檢測(cè)、錯(cuò)誤狀態(tài)報(bào)告
●狀態(tài)控制寄存器:MVBC配置
●主控單元:支持MVBC作為主設(shè)備或者從設(shè)備工作,支持隊(duì)列消息傳送
●設(shè)備地址讀取和儲(chǔ)存單元:硬件定義的設(shè)備地址可以被不同的值覆蓋
●地址邏輯:把CPU對(duì)MVBC內(nèi)部寄存器進(jìn)行訪問的輸入地址進(jìn)行解析;產(chǎn)生MVBC訪問TM的輸出地址
●總線復(fù)用、轉(zhuǎn)換單元:處理MVBC內(nèi)部的數(shù)據(jù)傳送
●中斷邏輯:支持16種中斷源;
●通用定時(shí)器:兩個(gè)定時(shí)輸出信號(hào),可提供給系統(tǒng)同步使用
●時(shí)鐘產(chǎn)生電路:產(chǎn)生所有MVBC工作的時(shí)鐘和計(jì)數(shù)器
2、JAMSC-B1060軟件設(shè)計(jì) 由于在MVB系統(tǒng)中,過程數(shù)據(jù),消息數(shù)據(jù),監(jiān)視數(shù)據(jù)是三種不同的通訊機(jī)制,因此,MVB系統(tǒng)軟件的模塊設(shè)計(jì)如圖6。 [align=center]
圖6:JAMSC-B1060系統(tǒng)軟件模塊[/align]
四、JAMSC-B1060軟硬件的聯(lián)調(diào)和集成 下面,以一個(gè)簡(jiǎn)單的例子來說明MVB系統(tǒng)的軟硬件的集成和驗(yàn)證。 過程數(shù)據(jù)在MVB系統(tǒng)中是周期性發(fā)送的數(shù)據(jù),其在本系統(tǒng)中的通訊機(jī)制如下:對(duì)于發(fā)送方,用戶應(yīng)用模塊將一個(gè)端口的過程變量發(fā)送給過程數(shù)據(jù)處理模塊,過程數(shù)據(jù)處理模塊按照邏輯端口的設(shè)置定時(shí)通過鏈路層接口模塊更新Traffic Memory當(dāng)中的相應(yīng)邏輯端口的數(shù)據(jù),此時(shí)發(fā)送方軟件的任務(wù)完成。發(fā)送方的MVBC硬件接收總線管理器BA定時(shí)發(fā)出的主幀,通過譯碼器解碼得到相應(yīng)的邏輯端口的值,通過查詢Traffic Memory相關(guān)的邏輯端口發(fā)送設(shè)置后將MVBC自動(dòng)設(shè)置為發(fā)送狀態(tài),將邏輯端口的數(shù)據(jù)作為過程數(shù)據(jù)從幀通過編碼器發(fā)出,如圖7所示: [align=center] 圖7:過程數(shù)據(jù)通訊示例[/align] 對(duì)于接收方,其接收過程與發(fā)送方相逆,接收方的MVBC硬件接收總線管理器BA定時(shí)發(fā)出的主幀,通過譯碼器解碼得到相應(yīng)的邏輯端口的值,通過查詢Traffic Memory相關(guān)的邏輯端口接收設(shè)置后將MVBC自動(dòng)設(shè)置為接收狀態(tài)將,在收到發(fā)送方發(fā)出的從幀后更新相應(yīng)邏輯端口在Traffic Memory的數(shù)據(jù)并發(fā)出中斷信號(hào)從而完成硬件的接收過程。接收方的軟件可以用中斷或定時(shí)查詢的方式通過過程數(shù)據(jù)處理模塊得到更新后的邏輯端口的過程數(shù)據(jù)
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